1. Field of the Invention
This invention relates to a method for fabricating complementary metal oxide silicon (CMOS) semiconductor devices having small geometries, as well as the devices produced by said method.
2. Description of the Prior Art
A typical prior art method for fabricating CMOS devices is depicted by the cross-sectional views of FIGS. 1a through 1c. As shown in FIG. 1a, substrate 11 typically comprises a silicon wafer having crystal orientation &lt;100&gt; and resistivity of approximately 3-5 ohm-cm. Upon the entire top surface of substrate 11 is formed a layer of oxide 12. Oxide 12 is typically formed to a thickness of approximately 500 .ANG., by a 40 minute thermal oxidation in 1000.degree. C. wet oxygen. A layer of silicon nitride 13, having a thickness of approximately 1500 .ANG. is formed on the surface of oxide 12. Silicon nitride layer 13 is typically formed by low pressure chemical vapor deposition, as is well known in the semiconductor arts, and described, for example, by Rosler in an article entitled "Low Pressure CVD Production Processes for Poly, Nitride, and Oxide", Solid State Technology, April 1977, pages 63-70 and by Brown and Kamins in an article entitled "An Analysis of LPCVD System Parameters for Polysilicon, Silicon Nitride and Silicon Dioxide Deposition", Solid State Technology, July 1979, pages 51-57.
Using suitable photolithographic techniques well known in the semiconductor art, oxide layer 12 and nitride layer 13 are patterned to mask the active areas 99a and 99b, while exposing the remainder of the surface of the wafer, as shown in FIG. 1a. This patterning is typically accomplished by etching those portions of silicon nitride layer 13 which are unprotected by the photolithographic mask with a CF.sub.4 plasma. Portions of oxide layer 12 which are exposed by the removal of portions of silicon nitride layer 13 are then removed, such as by etching in buffered hydrofluoric acid.
An implant of N type dopants is typically performed in order to establish the field threshold voltage at a desired level. For example, arsenic ions are implanted into the top surface of substrate 11, thus forming N doped regions 14. Of importance, the sandwich formed by oxide 12 and nitride 13 act as a mask, thus preventing the implantation of arsenic dopants into the active regions 99a and 99b.
As shown in FIG. 1b, a layer of photoresist 15 is applied to the surface of the wafer, and patterned to expose the to-be-formed P well 16. P well 16 is then formed, for example, by the implantation of boron atoms at 100 KEV. Of importance, photomask 15 absorbs the boron ions, thus preventing the implantation of boron ions into that portion of substrate 11 which is protected by photoresist 15, thereby selectively forming P well 16 within substrate 11.
Photoresist 15 is then removed. The arsenic dopants in N type region 14, and the boron dopants in P well 16 are then diffused at high temperature, thus establishing the desired dopant concentration profile. Field oxide 17 is formed by oxidizing those portions of the surface of substrate 11 which are not masked by the oxide/nitride sandwich formed by oxide regions 12 and nitride regions 13. Field oxide 17 is thermally grown by subjecting the wafer to wet oxygen (wet oxygen used for the growth of oxide typically comprises approximately 70% H.sub.2 O and 30% O.sub.2) at approximately 1100.degree. C. for approximately 200 minutes. The thickness of the field oxide is typically 1.2 microns.
During the dopant drive and the field oxide growth, arsenic diffuses both downwardly and, unfortunately, outwardly into the active area 99a. This effectively reduces the width W of the active area 99a, thus requiring that the active area 99a be originally defined by oxide 12 and nitride 13 to be larger than the desired channel width W.sub.N. Thus, the N channel width is originally defined to width X.sub.N, and is reduced to width W.sub.N by lateral diffusion of the arsenic dopants. Thus, (X.sub.N -W.sub.N) is the tolerance required when originally defining the active area 99a in order to be assured of an active area having width W.sub.N. This tolerance (X.sub.N -W.sub.N) is essentially wasted space on the surface of the wafer.
A similar problem of wasted space occurs in the formation of active area 99b. Because the oxide/nitride sandwich formed by oxide region 12 and nitride region 13 remains on the surface of the wafer when the P type implantation is performed, the oxide/nitride sandwich absorbs some of the P type boron dopants, thus resulting in a P well 16 having a lower dopant concentration in the active region 99b than in the remainder of P-well 16. Higher P type dopant concentrations in the periphery of P well 16 is desirable in order to provide increased isolation between adjacent devices, such as between the N channel device to be formed in active area 99a and the P channel device to be formed in active area 99b. During the high temperature diffusion and field oxide growth, the higher P type dopant concentration in the periphery of P well 16 is not only diffused downwardly and outwardly (away from active area 99b) but also diffused inwardly, thus encroaching on active area 99b. This encroachment, shown by the dashed line in FIG. 1c, effectively reduces the width of the active area 99b. Thus, the active area 99b must be originally defined by oxide region 12 and nitride region 13 to be of width X.sub.p, which is greater in width than the desired width W.sub.p of the active area 99b. As in the case with active area 99a, this tolerance (X.sub.p -W.sub.p) associated with the formation of active area 99b is wasted space on the semiconductor surface. As will be appreciated by those of ordinary skill in the semiconductor art, the actual values of the encroachment tolerance (X.sub.p -W.sub.p) is dependent on specific processing parameters, including dopant levels and the amount of dopant diffusion occurring due to diffusion and oxidation steps.